Arithmetic unit for digital computer



May 10, 1960 J. H. ALEXANDER ET AL 2,936,115

ARITHMETIC UNIT FOR DIGITAL. COMPUTER Filed Feb. 18, 1954 s Sheets-Sheet 2 V aw 99w INVENTORS James H. Alexander BY Arzfhur W Burke 4- W A/El MI E k L E s k L E. t.

May 10, 1960 ,1. H. ALEXANDER ET AL 2,936,115

ARITI-IMETIC UNIT FOR DIGITAL COMPUTER Filed Feb. 18, 1954 5 Sheets-Sheet 5 Owe/flaw Reset INVENTORS James h. A/exander Dona/d A. F/a'naer:

ATTORNEY Y Arthur W Burks May 10, 1960 J. H. ALEXANDER ET AL 2,936,115

ARITHMETIC UNIT FOR DIGITAL COMPUTER TIN T32 INVENTORS James H Alexander BY Arthur W Bur/(5 Dana/d ,4, F/anae/zs 4M '4. da /f ATTOP/VEY May 10, 1960 J. H. ALEXANDER ETAL 2,936,115

ARITHMETIC UNIT FOR DIGITAL COMPUTER Filed Feb. 18. 1954 5 Sheets-Sheet 5 INVENTORS James h. Alexander BY Arzhur W Burks Dana/a A. F/anaers ATTafNEY ARITHMETIC UNIT FOR DIGITAL COMPUTER James H. Alexander, New York, N.Y., Arthur W. Burks, Ann Arbor, Mich. and Donald A. Flanders, Chicago, Ill., assignors, by direct and mesne assignments, to the United States of America as represented by the United States Atomic Energy Commission Application February 18, 1954, Serial No. 411,294

Claims. (Cl. 235-164) The present invention relates to computing machines, and more especially to a novel method of and apparatus for performing arithmetic operations with binary numbers in a computing machine.

One frequently used method of representing algebraically signed binary numbers in an automatic computing machine is the fixed point 2-complement system, in which only numbers between +1 and -1 are directly handled by the machine. Numbers between 1 and +1 will be considered as being in range. In this system a positive or zero number is represented by a sequence of digits (0 or 1) correspondingto decreasing powers of 2, starting with the 0th power, i.e. 2, 2' 2. A negative number is represented by the complement of its absolute value. For example, a negative number a whose absolute value is b 1) is represented by 2-b, i.e. by 2+a. Since b 1, 2b 1, so every in-range negative number is represented by a positive number greater than one. Thus in the machine representation negative numbers are distinguished from positive and zero numbers by the fact that the former have "1 in the first place, while the latter have 0 in the first place. The digit in this first place is therefore called the sign digit.

One difliculty in prior multiplication devices using the complementing system for negative numbers is the necessity to make one or more of several alternative corrections to the product when one or both numbers are negative. For example, the product of a positive number q and a negative number -b should be bq. Yet in the machine, b is represented as 2b in binary notationand -bq by 2-bq. The machines product of -b times q is q(2b), or 2qqb. Therefore, a correction of 2-2q must be made to the machine product to obtain the desired representation of the product -qb whenever the numbers are multiplied together in a computer. But this correction factor cannot be used in the case where both numbers q and b are negative. In that case, the factors are represented as 2q and 2-b and the product by qb. Then the machines product would be 42q-2b+qb, so that a different, more complex correction, of amount (-4+2q+2b), is required to obtain the true product qb rather than the correction 2-2q, as in the former example. In other operating machines, there are alternative operations which must be performed, depending upon whether the multiplicand or multiplier is negative, and means must be provided to sense such conditions and direct operation accordingly. Hence it is evident that no universal correction factor can be built into the multiplication systems of the prior art. See a description of multiplication in the Institute for Advanced Study computer in Proceedings of the Association of Computing Machinery, Meeting at Toronto, Ontario, pp. 95-109, for example.

Another difficulty with automatic multiplication in a fixed point 2-complement system having a range of +1 and -l is that the numbers may go out of range, or overflow the design limits. Some means for detecting nite States Patent inns Patented May 10, 1960 such overflow is desirable; otherwise, quite large inaccuracies may result from the misinformation accumulated during a lengthy computing sequence. Mere inspection of the number in the machine registers will not detect the error, since there is no apparent difference between a positive number greater than one and a legitimate negative number, represented as greater than 1, as is above described. Moreover, extra carry or overflow which occurs when a number is formed that exceeds +1 or is less than -1 is, in effect, lost in conventional systems. Therefore, the only ways to detect illegitimate numbers in computers of the prior art were either to find how the suspect number was obtained by tracing back through the computation steps, or to provide a separate memory for each step and to inspect each memory continuously.

With a knowledge of the shortcomings of devices of the prior art, applicants have devised a novel method of and apparatus for automatic, accurate computation requiring only a single, constant multiplication sequence, easily and automatically included in machine operation, in which any errors due to overflow during computation may be instantly detected.

Accordingly, it is the primary object of applicants invention to provide a method of and apparatus for automatic, accurate computation.

Another object of the invention is to provide a novel arithmetic unit for a computing machine and means for directing computations therein according to a novel routine or algorithm, whereby automatic, accurate computation may be achieved and any machine errors due to computed numbers exceeding machine limits may be easily detected.

Other objects and advantages of the present invention will be apparent from a study of the following detailed in this-interpretation, since 0+q=a.

description of a preferred embodiment thereof, when read in connection with the appended drawings, wherein:

Figure l is a block diagram of the arithmetic unit and related portions of the control and memory systems of a computing machine incorporating the invention.

Figure 2 is a logical diagram showing in greater detail a selected portion of the arithmetic unit of Figure 1.

Figure 3 is a schematic drawing illustrating a preferred design of one of the denominationally ordered stages of the arithmetic registers shown in Figure 1.

Figure 4 is a schematic diagram illustrating a preferred design of certain arithmetic registers wherein special arrangement for overflow detection have been provided, as shown in block form in Figure 2, and

Figure 5 illustrates a single stage of a preferred adder circuit utilized in the arithmetic unit, shown in block form in certain other figures.

The mathematical basis of the electronic mechanisms to be described is the following: The 2-complement fixed point representation described above is capable of a slight generalization and of a different interpretation. Consider first a negative number a, =b, with 0 b 1. But a may be written in the form Since 0 b 1, 0 1-b 1. Thus a is represented as -1 plus a positive number less than 1. The conventional system represents a as 2+a=2b=l+(l-b), i.e. as +1 plus a positive number less than 1. Either system represents a by the same set of digits, and a register in the machine cannot tell the difierence. If, however, the wiring of the operations in the machine is arranged to treat the sign digit as negative, the treatment of the representation of the number may be made to be difierent. Positive numbers are equally well handled Along with this assent goes the minor, but useful, fact that the sequence of the digits 1.0 O, which is ambiguous in the conventional interpretation, is now consistently treated as representing l. e

The application of this interpretation to multiplication is as follows: Let q and b be iii-range numbers, positive, negative or zero. q is represented by q .q q',,-, where q=-q .2+q .2- +q .2- q i Then bq=-bq .2+bq .2 +bq,,.2-" v qnqn-1)- q1 qo If we set a =2* qn a =(a( )+bq,', ).2- q2) q1) then a =bq .2- +'bqg.2-" and bq=a -bq I The other mathematical notion used is the following. It is obvious that if a positive number, 0.a a@ a,,, is preceded by another 0 its value is not altered, i.e. 0011 a and 0.a a have the same value. The same holds true when the sign digit of a negative number is repeated, provided we interpret only the first digit as negative. E.g. /2=-1+V2 and is represented by 1.1. But /2=,-2+1+ /z, and hence may be represented by 11.1. Thus in-range numbers may be repre-' sented by doubling the sign digit. But a sequence of digits having two dilferent digits in front of the binary point must, according to our conventions, represent an out-of-range number. E.g. 01.a a represents (0.2)+1-j-a positive (or zero) number and hence is out of range. Similarly, 10.11 a represents (-1.2) +0+a non-negative number less than 1 nals travel the dotted lines. The arithmetic unit proper.

comprises a logical adder P and five binary registers S, A, A Q,'and Q The superscript u and subscript L indicate merely the physical location, upper or lower, of the registers in the computer structure. S is a storage register which receives information along control, hereinafter referred to as the MOSC, controls the sequence of transfer to and from the memory and to the arithmetic unit, and conveys information between that unit and the memory control. The dispatch counter dispatches the address contained in a received order to the memory, the control counter follows the progress of execution of the order, and the regeneration counter keeps track of menfory regeneration. These memory control counters may be interconnected by half-adders, not shown, which receive control signals from the MOSC along paths 116-118. The control system shown is of the type described generally in Preliminary Discussion of the Logical Design of an Electronic Computing Instrument, by Burks Goldstine, and von Neumann, Institute for Advanced Study, (1946). A typical control system of this type is specifically described in Proceedings of the Association for Computing Machinery, Meeting in Toronto, Ontario, pp. 95-109, andin the Sixth Interim Progress Report on the Physical Realization of an Electronic Computing Instrument, Institute for Advanced Study, (1951), pp. 70-98. See particularly pp. 73-82 and p. 18 of the last-named publication for descriptions of the shift counter and the clear selector,

herein called the dynamic programmer. For a further description of the functions of the control unit shown in Figure 1, se'e p. 196 of Proceedings of a Symposium on Large Scale Digital Computing Machines, August 3-5,

1 953, Argonne National Laboratory Report ANL-S 181,

paths 100, 101 from the Fast Memory or information storage system, and may be utilized to store the multiplier in a multiplication operation. The. accumulator registers A and A are interconnected through gates to permit shifting information directly up from A to A and directly down, down right, or down left from A to A as indicated by the solid lines 105, 102-104. The.

quotient registers Q and Q are also interconnected to allow shifting of information. Possible paths are from Q;, directly up to Q and from Q down right or down left to Q along lines 106-108. The accumulator and quotient registers are interconnected to allow transfer of information serially therebetween, as shown by the dashed lines 109-110. The multiplier may be taken from the memory and stored in the Q registers before multiplication along path 100. The adder P may comprise 41 binary stages connected to receive information from storage register S through complement gates 111 along paths 112, 113, and also from register A along path 114. Information from adder P may be transferred to register A alongvpath 115.

The arithmeticcontrol may be asynchronous, and cornprises a static programmer, a dynamic programmer, which generates the pfilse routine to program the-shift registers, and a shift counter, which may be a binary sealer. The dynamic programmer and shift counter units control the 'sub-cyele operation'of th'e arithmetic.

available from tl 1e Supt. of Documents, U.S. Government Printing Office, Washington, DC. a

The various registers in the machine, shown in block form in Figure 1, may comprise a plurality of distinct, denominationally ordered stages indicated by superscripts and subscripts 0 39. Registers Q, Q, and 8 may. contain forty such stages to accommodate words of fortybinary digits length, for ex mple. According to ourinvention, accumulator registers A and A and the adder P are provided with one extra stage, or forty-one 'stages each, with the extra stages, indicated by superbeing utilized together with thescr'ipt and subscript x, sign digit storage stages, indicated by the superscript and subscript 0," to detect overflow, and thus detect computatienal errors, as is more fully described hereinafter. Referring now to Figure 2, individual register stages are represented by rectangles containing the stage identificatioii. Of the upper accumulator register, the most significant digit stage A the least significant digit stage A, the sign di'git stage A, and the overflow stage A? are shown. The omittcdstages A A, as indicated b the dashed line between A and A are identical to A Corresponding stages of the lower accumulator register A and the adder P are shown direcn' elow those of register A. The sign digit, most significant digit, and least significant digit stages of the storage and Q quotient registers are shown as 8, S 5 Q Q and Q Q Q respectively. The solid lines extending from each numbered stage of A to corresponding and next adjacent stages of A indicate provision for shifting the contents of the stage in A in parallel down, down left, 0; down 'right to A of-A to the corresponding stage of A in'dicates provision fer shifting thecont'ents 'of' the stages in A up.

as A in par llel.

V a 4 I The line from each stage of A1, to a e 'coresponding stage in P, thatvfr om eachstage of S to a corresponding stage in P, and that from 'each stage'of P toal'corresponding stage in A likewise indicate provision for shifting information. also provided from each stage of Q tothe corresponding sgagecro from each stageof Q down right an'ddow'n The line fror'n e'ach stage Parallel shifting is,

gates 200-239, controlled by Logical "and" type gating circuits are indicated by small squares. The function of each transfer or shifting gate is indicated by the letter in the square. For example, U" represents gates for transfer up, D stands for a transfer down gate, L stands for a transfer left gate and R stands for a transfer right gate. In the conventional manner, logical and gates, represented by squares, are opened by the coincidence of two input enabling signals, as is more fully described below. Or gates are represented by circles, and indicate a gate wherein either or both inputs will actuate the output. Half-adder type elements are indicated by squares surrounding a plus sign. These devices deliver an output corresponding to the sign of two input signals. Thus if the first input is unexcited, the signal at the second input is reproduced at the output, but if the first input be excited, then the second input signal is etfectively inverted at the output. For example, half-adder 240 derives inputs from stages A and A and controls the state of overflow toggle 241 according as the inputs correspond or differ, as will be set forth more fully hereinafter.

Serial transfer of information from Q to A is provided through gate 243, controlled by an enabling signal on lead 244. Serial transfer of information from A to Q is provided through gate 245, controlled by an enabling signal on lead 246, and through gate 247, controlled by the signal on enabling lead 248. Information is gated in parallel from the memory M M into SS along the path 101 of Figure 1 by a signal on lead 249, and into Q along path 100 (Figure 1) by a gating signal opening the In gates in the respective Q stages. A Complement enabling signal on lead 640 opens the half-adder type gates 600-639 between S and P.

Half-adder gates 251, 254 receive inputs as indicated and serve to control the performance of division commands. overflow operations, their functions will not be described.

A typical single stage of one of the arithmetic registers is shown in Figure 3. The stages may be based on symmetric or asymmetric toggles, but the latter are preferred. The register is arranged in two banks, A and A each corresponding stage comprising an upper toggle, a lower toggle, and interconnecting gates and drivers. The upper toggle comprises triodes 301, 302. The plate of triode 301 is coupled through plate resistor 303 to a clear lead 304 from a source normally at +110 volts D.C., the grid is grounded, and the cathode is coupled through resistor 305 to a source of +300 volts DC. The plate of triode 302 is coupled directly to a source of +150 volts D.C., the grid is coupled to the junction of resistors 307, 308, and the cathode is common to that of triode 301. One terminal of resistor 307 is coupled to the plate of triode 301, and one terminal of resistor 308 is returned to the source of 300 volts. The lower toggle comprises triodes 309, 310 and associated resistors and power supplies and is identical to the upper toggle.

Tubes 313, 314, and resistor gate 315 constitute the transfer up circuit. The grid of tube 313 is coupled to the junction of resistors 311312 and will assume a potential of either +30 volts or 8 volts, depending on the state of the lower toggle; that is, which one of tubes 309, 310 is conducting. Assuming that tubes 301, 310 are initially conducting, it is apparent first that the two toggles are in different states, and second that the grid of tube 313 is at its higher potential, since no current is flowing through tube 309 and its plate resistor. The cathode potential of tube 313 is determined by the voltage on lead 316.

Normally the lead is maintained at 100 volts D.C., so that tube 313 will conduct independently of its grid potential. A transfer up pulse on lead 316 raises that lead potential to about 35 volts D.C., as is shown in the waveform T. The new, higher potential at its cathode will cutoff tube 313 only if its grid is at the lower of its Since they do not relate to the multiplication or two possible potentials. But as aforesaid the grid is at: its higher potential, so the tube remains conducting, and the cathode potential will remain high, allowing the potential of the grid of tube 314 to rise with the transfer pulse. Tube 314 will then conduct and the potential of its cathode and the common cathode of the upper toggle will rise, causing tube 301 to cut off. Tube 302 will then conduct, due to the rise in its grid potential. When the common cathode potential is allowed to fall by removal of the transfer up pulse from lead 316, the grid of conducting tube 302 is higher than ground, so tube 302 will continue to conduct. Thus the state of the upper-rank toggle has been changed to conform with that of the lower-rank toggle, or, in computer terminology, information has been transferred from A up to A.

The transfer-in gating circuit comprises toggle driver 317, gating lead 318, resistor gate 319, and gate driver 320, and is similar in operation to the above-described transfer-up circuit.

The transfer right, transfer left, and transfer down circuits operate similarly. The tubes 321-323 are the toggledriver tubes, and may have their cathodes tied.

to a common lead 324 which is coupled to the common cathode 306 of the lower toggle. Each tube is supplied from a separate source of +110 volts D.C. Respective resistor gates 325, 326, 327 are provided with corresponding gating leads 328, 329, 330 to which are coupled respective gate driver tubes such as tube 331. The other two gate drivers are not shown, as they are associated with the next adjacent register stages. The gate drivers are conducting or non-conducting, depending on the state of the corresponding toggle to which their grids are coupled, and the cathode potentials of the gate drivers determine the potential at one terminal of the respective resistor gate, as above-described. To efiect a transfer right, left,

or down, the corresponding gating lead is supplied with a transfer pulse going from to -l3.5 volts, resulting in a driving of the lower toggle to the appropriate state.

Clearing the toggles to a predetermined state is accomplished by lowering the plate voltage of the left-hand tubes of the toggles (tubes 301, 309), thus lowering the grid potential of the right-hand tubes 302, 310, below cut-off and causing tubes 301, 309 to conduct. Minimum clearing time is about 1 microsecond and transfer time is about 1.2 microseconds.

The adder P shown in Figure 1 may be of conventional construction of the type wherein binary numbers may be transferred in and out in parallel, and wherein the transferred number is added to the previous contents of the adder automatically upon such transfer in. The number of individual adder units required is equal to the maximum number of digits of the numbers tobe handled, or 40 in the embodiment described, plus 1 extra stage P for overflow detection.

7 A sample stage of a preferred adder circuit, not designed by the present inventors, is shown in FigureS. For other similar, suitable devices, see High-Speed Computing Device, Engineering Research Associates, 1950, chapter 13.

Design of the present adder is based on the fact that in adding binary numbers, a carry is produced by a pair of ones, and will continue if either of the next pair of digits added is a one. The carry will stop only if both digits are zeros. Therefore, the present adder senses the pairs of digits and produces a carry at every stage until two zeros appear, at which stage it stops the carry. A gate is arranged so thata carry entering from the right will continue through the gate, or can be started by the presence of two ones in this stage, or can be stopped by the presence of two zeros in the stage.

Moreover, the single stage shown provides, in addition to the carry information, the sum of the numbers introduced. If the two numbers added are alike, the carry.

input number is equal to the sum. If the two numbers 7 are unlike, the carry input number is inverted and is then equal to the Referring new to Figure 5, input 501 derives a signal fioni tlie toggle hblding the resident digit, while input 502 dei'ives a signal corresponding to the incident digit. Gathode 513 will follow the higher of the two grids, and will rise in potential if a one signal is impressed on either 'input. n The incident digit input signal is also impressed 'on grid 504:, while the voltage at point 505 is impressed an grid 506. The carry input 503 is impressed on grids 507--'-50 9.

To 'illusti'ate the operation of the stage, assume a l resident digit, afl incident digit, and a carry in. Then inputs 501, 502, and 503 will each be at +10 volts. Point 505 on the voltage divider and grid 506 will be at Volts. Tube 515 "will conduct because of the positive signal on grid 504, thus raising the cathode potential to above 0 volts. Therefore, tube 512 will be cut off, and grid 509, which is connected to theplate of tube 512 through a voltage divider network, will assume its highest potential. Since grid 509 is above cut-off, and the cathode line 518 will rise to +10 volts, representing a 1. Carry out-put line 519 will be at +10 volts if a positive signal appears at either grid 507 or grid 510. Since both grids are at +10 'volts, line 519 assumes that potential, representing an output carry signal.

- To further illustrate operation of the circuit, if the resident digit is "1," the incident digit 0, and no carry enters line 503-, then a 1 should be set up on line 518 and no carry on line 519. Since cathode 513 follows the higher grid, itassumes a potential of +10 volts, raising grid 506 to 0 volts, dropping the plate potentialfof tube 512 to 'a low value, cutting off tube 525. Grids 504, 510 assume -30 volts, cutting on tubes 515, 520. Line 503 assumes 30 volts, cutting off tube 521, allowing diode 522 to conduct, lowering the potential at grid 507 to cutoff tube 523. Since tubes 520 and 523 are both cut off, output line 519 will assume 30 volts, the signal for no carry. Diode 524 also conducts, holding grid 509 below cut-off. But the tube including grid 516 conducts, raising the potential of line 518 to +10 volts, the signal for "1.

Operation of the interrelated computer units above described is directed by a series of timed pulses from a control system. Multiplication of a 39-digit number b by a 39-digit number q according to novel method we have invented, involving the algorithm bq=a bq is dcscribed in detail below. Reference is made to the numetals on the typical stage of Figure 3 for clarity, and to the logical diagram of Figure 2 where necessary.

Step 1: Multiplier q is selected from its position in memory Mg, M in the conventional manner and delivered through respective in gates to shifting register Q in the form q .q q q where g the sign digit, is 1 for a negative number and-0 for a positive number. To accomplish such transfer, a control pulse is delivered to the respective T leads 318 of the Q stages in order to open the IN gates.

Step 2: Arithmetic accumulator shifting registers A and A are cleared to 0 by pulsing clear leads 30.4, 332.

Step 3: Multiplican'd-b is selected from the Memory M and placed in register S? in the form b .b b bag by pulsing lead 249 to open gates 200-239. From S, b autornatic ally enters adder P through the half-adder gates 600639, as described supra. V s, I I

Step4; The product of b times the least significant digit q a gJis effectively taken and "putin adder P where it is added to the ediite'nts ofA now zero. This is accomplished by the "control unit, which receives lead 489 from Qaa and in response to 'the signal thereon directs "either ('izltransferfoftlie contents of "adder P to accumulator n w pulsing'gate control leads 699 739 if Q "=1,'or (b) no transfe'r if 125 0, the conventional manner dsettbd in the Sixth interim Prdgr'ess Report, -'supra,

in connection Figure 12 (pa e 18) of the publicanon.

Step It were a transfer as A in step then the 'c'onfe ts '01P, new f Fb qgg, we e transferred to A? tli'rio'ugh respective "inp ut gates I along the paths 259-299; Gohti-bl enabling pulses onleads 699-739 openthose gates. If the partial sum from P was not transferred (q 9i, then the contents or A are shifted v A along paths 749%789 and through up gates U enabling pulses from control fon leads to open those gates, and agaisa contains -l bq I Step 6: Simultaneously either operation in step 5', multiplier q is transferred from Qgto Q along paths 450 439 by enabling pulses from control on leads 650 "689 to open the npfigat'es. I I H V Step 7: The product now iniA is effectively niutiplied by 2- by a dowr i-right shift from A" to A along pathsf849-j l, through'respctive Rf gates, so that Q6 and "Af now hold 1 211111 92 1. The sign digit from A in addition to being shifted down-right along lead 849 is also 'shift'e'd down to register A along lead 448. I

Step 8: The multiplier is simultaneously positioned for its next operation by a like shift from Q} to Q through the R gates in the register alongthe 'p'aths corresponding to path 890 from Q to Q 5, 'so that 2155', the 38th digit of 9, now is in the 39th register stage (2 Step 9: The adder P 'rec'eivesfthe partial product from register A which is connected directly to jadd'er P as shown in Figure 2, and adds it to the ninltiplicand from register S, which is also, connected to P through half-adders 660-639, the addition process being described in connection with Figure 5. 7

Step 10: The contents [(bq )2- +bq of P, or the contents [(bq )2- of A are again transferred to A as in step 5, depending on whether the digit in Q3, is l or 0 by a signal from control to either the In gates or Up gates in A.

Step 11: Multiplier q is transferred from Q to Q" along paths 450489 and through the Q Up gates simultaneously with step'10 by pulses from control on leads 650-689. I

Steps 12 and 13: The partial product is multiplied again by 2- and q' is shifted into Q3 by down-right shifts from A to A and Q to Q;,.

Step 14: The above steps 9-13 are repeated until the most significant digit of the multiplier, q has been utilized, and q the sign digit, is in Q 9. The shift counter stops repetition of the steps after 39 multiplier shifts, in the conventional manner.

Step 15: Then, according as q' is (a') 0 "or (b) 1, the control will (a) do nothing to the product in P, the In gates to 'A being closed, while the contents of A are transferred through Up gates to A, as instep 5, or (b) transfer the contents of P to the accumulator through the In gates to A, 'as in step 4. The shift counter output after 39 steps energized the complement gate lead 640 to gates 600-639 between S and P, also adding 1 to P so as to form a true binary complement.

Gates 600-639 are, in effect, a pair of alternate paths for information, one of which transmits it unchanged while the other effects inversion. Enabling lead 640 opens the latter paths to admit the complement of b ime I, thus effectively subtracting (bq from the product 'storetl there, and forming {W -m which is the desired product according to the above-stated algorithm.

The interniediate sums formed may be out of rsnge, but will not trip the overflow toggle 241 because they are always transferred down-right, while the toggle maybe tripped only on down and dow'nleft shifts. Since b and q are both less than 'lan'd 'equ'al to 6r greater tl 'an '-'-1, their prdmie't 'is aiways between +1 and l except in case Ir qi +1. In that easathe subtraction step above will set the overflow toggle as "the result passes down has to A3, sense the voltage levels on iea'tts J 256, 257 will be ditterent, thus indicating thatthe product held is out of range.

Unbiased round-ofl may be readily obtained by inserting a 1 into the most significant digit stage A, at the same time the rest of A is cleared to 0. Provision is made for clearing that stage to 1 by lowering the plate voltage of the right-hand tube in its toggle. After 39 shifting steps the 2- has been multiplied by 2' so that in effect 2- has been added to the product, and A contains 39 digits of bq plus 2-, which is an accurate, unbiased round off.

As has been mentioned above, three extra stages A, A and P are provided in the registers A, A and P, and are connected respectively to the sign digit-stage A, A and P A digit b identical to the sign digit b of the stored number is inserted automatically into P and P by virtue of the direct connection 258 between half adder 440 and P,,. From P and P the information is transferred up to A and N along paths 259, 260 and through the In Gates and down to A and A through the down gates along paths 448, 449.

If at any time a down or a downleft shift operation in the computer involves a carry between P, and P on lead 447, such that the sign digit in P would change, the associated arithmetic register stage A will change and differ from A a special toggle 241 is actuated by half-adder 240 when A and A differ, to give warning that overflow has occurred. This toggle may be provided with a neon tube for visual inspection at the end of each computation, or as often as desired during a particular operation. In addition, it may be used to provide a signal along lead 242 to a warning light or audible alarm, or to stop the computer operation, if desired.

If a number greater than /2 is multiplied by 2 by shifting left, an overflow will result, because the most significant digit b stored in A and P is binary 1." Since a left shift must go from A up to A, then down left to A along the paths shown on the figure, the l stored in A is first transferred up to A Then the l is transferred down-left, flipping toggle A to its opposite state. When the number in A is next transferred up to A, the 1 now stored in A will cause A to change state, so that it will differ'from A". The half-adder circuit 240 is actuated by the change in A through lead 256, and delivers a signal to set the special toggle 241 accordingly. Similar remarks apply to the detection of overflow resulting from multiplying a number less than /2 by 2.

Referring now to Figure 4, the overflow toggle 241 may comprise a twin-triode tube 400 having a grounded common cathode and separate anodes energized from a source of potential through respective anode resistors. Grid 401 is disposed in the input circuit, grid 402 receives reset signals, and anode 403 is disposed in the output circuit. Triode tube 464 is energized from a separate source of potential and receives input signals on its grid 405 from anode 403. Neon bulb 450 is resistively coupled between cathode 406 and ground so that it will conduct only when tube 404 conducts suficiently to raise cathode 406 above the firing potential of the bulb. For resetting the toggle, an external reset pulse going from +30 to 30 volts is impressed on lead 409, which is coupled to one grid 411 of twin-triode tube 410, the opposite grid of which is grounded. A negative output signal is taken from anode 412 as the right half of tube 410 conducts and coupled to grid 405 to cut oflf tube 404, thereby transmitting a negative pulse to grid 442 through condenser 407 to cut ofi the right half of toggle 400, thus resetting it to the desired state.

Signals from stages A and A are taken on leads 256, 257 and applied to respective grids of twin-triode tube 413. Both halves or sections of the tube are energized from a common source of potential through respective anode resistors and a common cathode resistor 420. Triode tube 419 is energized from a separate source of potential through anode resistor 433 and cathode resistor 420 while its grid is grounded. Leads 256, 257 are also coupled through a mixing network including diodes 414, 415 and resistors 416, 417 to the grid of triode tube 418, the cathode of which is grounded while the anode is coupled to the anode'of tubes 419, 421. The grid of tube 421 is coupled to a positive and gate including a pair of diodes 434, 435 having respective cathodes coupled to gating leads varying from --20 to +20 volts and their plates coupled together to a source of volts. The common anode lead 422 is coupled through a voltage divider 423 to the grid of triode 424, the cathode of which is grounded while the anode is coupled to the grid of tube 425 and to a source of potential through resistor 426. The'anode of tube 425 is coupled to a source of energizing potential, while the cathode 420 is returned through resistors 427, 428 to a source of negative potential. Condenser 430 couples the cathode 429 to grid 401, which is also coupled through a limiting resistor to the junction of cathode resistors 427, 428. The grid of tube 431 is also coupled to that junction, while the anode is coupled to an energizing source and the cathode is returned through a resistor to a source of negative potential. An output lead 242 is coupled to the cathode for deriving an overflow negative pulse as toggle 400 flips, for utilization either to stop computer operation, actuate an alarm, or as otherwise may be desired.

In operation, upon occurrence of overflow within the arithmetic unit A registers, toggle A will will change state, altering the potential on lead 256 so that it differs from that on lead 257. Assuming that prior to the overflow both leads 256, 257 were operating at -25 volts, then lead 256 would assume a potential of +25 volts. The right half of tube 413 will conduct, raising the oathode potential above ground, thus cutting olf tube 419. Tube 418 is cut off because the cathode of diode 415 remains at 25 volts, holding the grid potential of tube 418 at that voltage, which is below cut off. In normal operation, both diode cathodes are held at +20 volts, their plates are at +20 volts, and tube 421 conducts through resistor 433, dropping the grid voltage of tube 424 below cutoff. However, upon occurrence of a transfor down (Td) or down-left (T signal, one of the diode cathodes fall to -20 volts, the plate follows the lowest cathode down, and tube 421 cuts ofi. No current flows through resistor 433, so that lead 422 rises to substantially volts and tube 424 begins touconduct, drawing current through resistor 426 and cutting off tube 425. Cathode 429 will then fall in potential, and will pull grid 481 negative through the coupling condenser, cutting off the left section of the toggle. Tube 431 will also be cut ofl, driving lead 242 from +30 to +30 volts; grid 405 will be driven positive, making tube 404 conduct, raising the potential of cathode 406 and associated grid 402, thus allowing the right half of toggle 400 to conduct, and firing neon bulb 450.

If, on the contrary, both leads 256, 257 are initially at +30 volts, both sections of tube 413 will conduct, raising the cathode potential suficiently to cut off tube 419. But tube 418 will conduct because of the positive potential impressed on its grid through the mixer diodes, and will draw current through resistor 433, lowering the potential of lead 422 sufliciently to cutting off tube 424. When lead 256 drops in potential to --25 volts, it will cut off the right half of tube 413, lowering the cathode potential somewhat, but not enough to allow tube 419 to conduct. Diode 414 will conduct more heavily, pulling the grid of tube 418 down to 25 volts, which is below cut off, so that no current flows through resistor 433. Lead 422 then will rise to substantially +150 volts, tube 424 will conduct, tube 425 will be cut ofl, and the left half of toggle 400 is cut off.

Since by the reset action above described the right half of the toggle was cut off, it is apparent that cutting off the left half of the togglefiips it to the other stable state.

Thus anoverfiow in the A registers both actuate; the,

11 neon bulb indicator and produces a negative overflow pulse for further utilization as desired.

It will be apparent from the above description that we have invented a novel method of operation of an arithmetic unit of a computing machine and have provided novel apparatus for carrying that method into execution, whereby the 2-complement fixed point system of representation may be utilized, yet the ambiguities and possible error sources of the prior art have been eliminated without recourse to elaborate additional functional units for making multiplication corrections for overflow detection, and the like.

What is claimed is:

1. In a digital computer provided with a plurality of denominationally-ordered, multistage binary registers including a first n-stage register to receive the multiplicand and a first n-stage shifting register to receive the multiplier, where n is a selected number, means for shifting said multiplier successively toward the lowest-ordered stage, shift counter means to provide a completion signal after n-l shifts, and digit sensing means coupled to said lowest-ordered stage in said first shifting register for generating first or second signals according to the stable state of said lowest-ordered stage, the improvement comprising: a double rank shifting accumulator register having n+1 stages; a binary adder including an adder stage associated with each accumulator register stage, each adder stage being provided with a first input coupled to a correspondingly ordered stage in a first rank of said accumulator register, a second input, a carry input coupled to the next-lowest ordered adder stage, a carry output connected to the next-highest ordered adder stage, and a sum output connected to a correspondingly ordered stage in 'a' second rank of said accumulator register; a halfadder associated with each stage of said multiplicand register, each ha1f-adder being provided with first and second inputs and a sum output, a common control lead energized by said completion signal and connected to each of said first inputs to said half-adders to provide first binary input signals, said second inputs of each halfa'dder stage being connected to the correspondingly-ordered multiplicand register stage to derive therefrom second binary input signals, said sum output of each stage being coupled to said second input of the correspondinglyordered adder stage; means to set the two highest-ordered stages in each rank of said accumulator register to the same stable state; respective first gate circuits connected between corespondingly-ordered stages of said first and second ranks and provided with an input energized by said first control signals; respective second gate circuits connected between respective sum outputs of said adder and the correspondingly-ordered stage in said second rank and provided with an input energized by said second control signals; a second half-adder provided with inputs connected tothe two highest-ordered stages of one rank of said accumulator register and a sum output for providing an overflow signal only when said stages assume different stable states.

2. In an arithmetic unit for a computer comprising a plurality of storage register, one of said registers being a double rank accumulator register, and a multistage adder, each of said registers comprising a plurality of discrete bistable stages for storage of the binary digits representing a number and one stage per register for storage of a binary digit representing the algebraic sign of the number,

- the improvement comprising: a pair of additional bistable stages identical to said one register stages and coupled to respective sign storage stages in respective ranks of said one register; means coupled to said sign stages for setting said additional stages to an electrical state corresponding with that of the respective sign storage stages prior to performance of an arithmetic operation; and means coupled to that additional stage coupled to said one register in a first rank and to the sign storage stage of said first rank said one register to derive signals thereinterconnecting gating circuits, the improvement comprising: a first bistable sign stage coupled to the highestordcred number stage of said register; an additional bistable sign stage coupled to said first sign stage to form the highest-ordered stage; means for setting all said stages to a corresponding initial condition; an additional bistable toggle circuit having input and output circuits associated therewith; and a switching circuit having two input circuits and an output circuit associated therewith, the output circuit of said switching circuit being coupled to the input circuit of said additional toggle to actuate said toggle, one input circuit of said switching circuit being coupled to the highest-ordered stage in said register to derive a first potential therefrom, the other input circuit of said switching circuit being coupled to the second highest-ordered stage in said register to derive a second potential therefrom, said switching circuit being provided with a half-adder circuit connected to both said inputs to produce an output signal to actuate said toggle only when said first and second potential differ.

4. The apparatus of claim 3 wherein said additional toggle and its associated circuits comprises first and sec ond electron tubes having respective input grids, output anodes, and a common cathode, a gas discharge glow tube, means coupling said glow tube to said toggle for firing said glow tube only when a selected said second electron tube is conducting, and means coupled to one of said grids for causing said first tube to normally conduct; and said switching circuit comprises third and fourth electron tubes having input grids and a common output cathode, two input leads coupled to said grids, a fifth electron tube having an input grid and an output anode, respective diodes coupling said input leads to said fifth tube grid, a sixth electron tube having a cathode coupled to the cathode of said third and fourth tube, a voltage divider coupled to the anode of said fifth and sixth tubes and to a source of D.C. potential, a seventh electron tube having an input grid coupled to a point on said divider normally below cut-ofi potential and an output anode, and an eighth electron tube having an input grid coupled to said seventh tube anode and an output cathode coupled to the grid of said first tube to cause said first tube to conduct only when said eighth tube conducts, whereby only a substantial difference in potential between said input leads efiects an increase in current flow through said divider, thereby raising the potential of the grid of said seventh tube causing it to conduct, cutting oif said eighth tube, cutting ofi said first tube, and firing said glow tube.

5. An arithemtic unit for obtaining the product of two binary numbers, each including a sign digit and n-l magnitude digits, each number being represented by appropriate settings of binary storage elements arranged in registers, comprising: multiplicand, multiplier, and accumulator denominationally-ordered registers, said multiplier and accumulator registers being shifting registers, said accumulator register being provided with two corresponding ranks of binary storage elements, and each register being provided with parallel inputs and outputs; a denominationally ordered parallel adder having first digit inputs connected to one rank of said accumulator register, second digit inputs, and outputs; respective halfadder stages each having a first input coupled to said output of a corresponding stage of said multiplicand register, a second input, and a sum output coupled to said second digit adder inputs; respective first sets of gates coupling said adder outputs to inputs of the second rank of said accumulator register; respective second sets of gates coupling the outputs of said one rank to inputs of said second rank of said accumulator register; respective means coupling the output of the lowest-ordered stage of said multiplier register to said first and second sets of gates to energize one set of gates responsive to a first binary output therefrom and the other set of gates responsive to second binary output therefrom; means for periodically shifting both said shifting registers toward the lowestordered stage; and counting means coupled to one of said shifting registers for providing an output completion signal after n-l shifts and provided with an output connected to said second half-adder inputs to energize the same, allowing the complement of the multiplicand to enter said adder, said output also being connected to said shifting means to disable the same after n-l shifts.

References Cited in the file of-this patent Functional Description of the Edvac; vol. 1, page 4-7; vol. II, Fig. 104-3LC-1. Nov. 1, 1949.

Wilkes: The Edsac-an Electronic Calculating Machine, Journal of Sci. Inst. and of Physics in Ind. (British), December 1949, pages 389, 390'.

Engineering Research Associates, High-Speed Computing Devices, 1950, page 271.

Argonne Nat. Lab., Progress Report on the Argonne- V 14 Oak Ridge Digital Computer, March 5, 1951, pages 22a, 22b, 24 to 26, 38, 44, and in Fig. HI. (11 (page 39), relied on.)

ORDVAC Manual, Illinois University, Ad104961, October 1951, complete copy at ASTIA section, Lib. of Congress; pages ii-iv, 5 to 7, 9 to 11, 14, 15, 23 to 25, to 66, 129 to 132 relied on.

Estrin, Description of the Electronic Computer at the Institute for Advanced Studies, Proc. Assoc, for Comp. Mach., September 1952, pages 101 and 109.

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Robinson: Multiplication in the Manchester University High-Speed Digital Computer, Electronic Engineering, January 1953, page 6.

Buchholz: System Design of the IBM Type 701 Computer, and Ross, Arithmetic Element of the IBM Type 701 Computer, both articles in IRE Proc., October 1953, pages 1266, 1268 to 1270 and 1288 relied on. 

